Thin-layering and High Capacitance: “Stacking” Capacitors Together

[Opinion] The core approach to achieving high capacitance in MLCCs is to “increase the number of dielectric layers while making them thinner.” Thinning and miniaturization together define the cutting edge of industry technology, with the key challenges lying in thin‑layer printing processes and lamination yield. Moreover, as dielectric layer thickness continues to decrease, the product’s reliability margin becomes increasingly constrained.

I. Why does capacity depend on “stacking”? The capacitance of a single‑layer planar capacitor is given by the formula C = ε·A/d. In a multilayer structure, N layers are connected in parallel, resulting in a total capacitance approximately equal to C ≈ N·ε·A/d. With package dimensions fixed, there are two ways to increase capacitance: first, by modifying the dielectric material to raise its dielectric constant ε; second, by reducing the thickness of each layer to decrease the interlayer spacing d while simultaneously increasing the number of layers N. Today, high‑capacitance multilayer ceramic capacitors employ single‑layer dielectrics with thicknesses as low as submicron or even down to the hundred‑nanometer scale, and they can comprise hundreds or even thousands of layers—precisely through this stacked architecture that higher capacitance values are achieved.

II. Challenges in Thin-Film Processing. The thinner the dielectric layer, the more stringent the requirements for powder particle-size uniformity, consistent printed-layer thickness, and interlayer alignment accuracy. Ultra-thin layers are highly susceptible to pinholes, interlayer shorts, and edge defects, directly reducing yield. Moreover, in high‑performance capacitor devices, even minute internal micro‑shorts can cause failure probabilities to rise exponentially, and such faults are difficult to detect through conventional visual inspection. Consequently, statistical process control and accelerated screening methods must be employed.

III. Concurrent Advancement of Miniaturization and High Capacity. Achieving µF‑level and even tens of µF capacitance in miniature packages such as 0201 and 01005 has become a critical requirement for smartphones and wearable devices. However, this trend is pushing thin‑film, multilayer, and terminal‑electrode technologies to their physical limits, imposing increasingly stringent reliability‑design requirements—such as resistance to bending, thermal shock, and delamination—while also driving up the cost per capacitor.

IV. Cutting-Edge Technologies and Competitive Boundaries. Large‑capacitance multilayer ceramic capacitors (MLCCs) of 100 µF and above are widely used in package sizes such as 1206 and 1210, competing with solid‑state and polymer capacitors. Their advantages include low equivalent series inductance (ESL) and excellent high‑frequency performance; however, they also suffer from limitations such as capacitance degradation under bias voltage and temperature drift. To ensure that high‑capacitance variants meet automotive‑grade requirements, they must pass reliability tests—including high‑temperature high‑humidity (THB), thermal cycling, and mechanical stress—making these assessments a critical entry barrier.

◆ Perspective · Trade-offs: Thinning processes can enhance volumetric resolution and volumetric efficiency, but they come at the expense of reliability margins. In practical applications, these trade-offs must be mitigated through derating design, material modifications, and stringent process‑window control—rather than simply pursuing capacitors with higher nominal values. For high‑capacitance devices, “effective capacitance under bias conditions and reliability verification data” should serve as a rigorous selection criterion.